A novel design of CMOS dynamic latch comparator with dual input single output with the differential amplifier stage is presented in this paper. The designed dynamic latch comparator is required for high-speed analog-to-digital converters to get faster signal conversion and to reduce the power dissipation, which is immune to noise than the previous works. In this paper, the design and analysis of a latching comparator using charge sharing circuit topology is illustrated to achieve low power and high-speed operation. The proposed circuit is designed using CEDEC 0.18 µm CMOS process. The simulated results shows that, 100 MHz clock frequency with the power supply voltage (VDD) 3.3 V and input range 3.3V produce the desired output signal. The topology of the proposed design is able to minimize the propagation delay and power consumption with the improved performances than other research works. Moreover, the different capacitor value and the transistor lengths produced the faster output, which is suitable for the successful operation of the ADC.

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